In many VLSI integrated circuit devices, there is a need to fabricate transistors that have different electrical performance characteristics. For example, SRAM cells suffer stability problems as the cell size is reduced. To function properly, the SRAM memory cell, when charged, must hold a voltage level, either high (logic 1) or low (logic 0). When reading data from the cell, the charge pulse generated as the pass transistor turns on must not flip the voltage level at the storage nodes. To stabilize the cell, the driver transistors are fabricated to have a higher current gain than the pass transistors. Usually, the current gain relationship is controlled by adjusting the width-to-length (W/L) ratio of the driver transistors relative to that of the pass transistors. The ratio of the W/L values of the two sets of transistors is known as the cell ratio and is commonly specified to be at least 3.0 or larger.
The physical adjustment of the W/L ratio for an MOS transistor requires a dimension change in either the width or the length of the gate electrode. In a VLSI circuit, where component sizes are typically reduced as much as possible, a constraint is placed on the maximum dimension of both the width and the length of the gate electrodes used in a circuit. This constraint limits the ability of a circuit designer to affect a parameter, such as the cell ratio. The cell designer is not free to arbitrarily select large values for one dimension relative to the other dimension in order to achieve the desired W/L ratio.
Recognizing a need to control the performance characteristics of one MOS transistor relative to that of another by means other than changing physical dimensions of the gate, technologists have developed other methods to control transistor performance characteristics. In one method, the control of the current gain of a pass transistor relative to a driver transistor is achieved by changing the doping concentration in a source-drain region. The gain of the pass transistor is reduced by omitting the N.sup.+ source region when forming the pass transistor. While this method is effective in changing current gain, the alteration of the source electrical field relative to the drain electric field can result in asymmetric behavior and poor overall performance. In another method, the thickness of the gate dielectric is increased in one set of transistors relative to the thickness of the gate dielectric of the other set of transistors. For example, the thickness of the gate dielectric layer is made thicker in the pass transistors relative to the gate dielectric thickness in the driver transistors. The pass transistors each having the thicker gate dielectric layer have a lower current gain than the driver transistors. While changing the dielectric thickness is effective is altering current gain, additional high-precision processing steps are necessary to obtain an exact dielectric thickness differential between the two sets of transistors.
Although the techniques described above overcome the limitations inherent in adjusting the dimensions of a gate electrode in a VLSI circuit, still more exact control of the current-gain parameter is needed to meet the demands of ever smaller circuit designs. In achieving a desired current gain differential, the method used must not result in abnormal transistor performance, such as asymmetric performance characteristics, and must be readily manufacturable.